Phase-locked loops (PLLs) are often used as clock regenerators or frequency synthesizers in digital systems. PLLs have a wide variety of applications in areas such as communication devices and other types of digital electronics. FIG. 1 illustrates a conventional PLL 100. PLL 100 functions to maintain a clock output 110 in phase alignment with a reference clock 120. The clock output is fed back through a loop divider 130 to form feedback signal 105 and compared with the reference clock in a phase detector 140. Based upon this comparison, the phase detector adjust the pulse widths of an up signal and a down signal 145 (denoted as UP/DN) based upon whether the clock output lags or leads in phase with respect to the reference clock. A charge pump 150 receives the up and down signals and changes the capacitively-stored charge in a loop filter 160 accordingly.
FIG. 2 illustrates a simplified view of the functional relationship between the charge pump and the loop filter. The charge pump acts as a current switch to either sink or source a current I from a capacitor C in the loop filter using current sources I1 and I2. Should the up signal be pulsed before the down signal, the current switch couples a terminal S1 to the loop filter so that the current I from source I1 charges the capacitor. As a result, the voltage across this capacitor increases. When the down signal is subsequently pulsed, the current switch decouples from terminal S1 such that the raised voltage is held until the next up/down pulse cycle. As seen in FIG. 1, this raised voltage will then drive a voltage-controlled oscillator 170 to increase the frequency of the clock output to reduce the phase lag that prompted the pulsing of the up signal. Referring again to FIG. 2, should the down signal be pulsed before the up signal, the current switch couples the loop filter to a terminal S2 so that the current I from source I2 is sourced from the capacitor in the loop filter. As a result, the voltage across the capacitor decreases. When the up signal is subsequently pulsed, the current switch decouples from terminal S2 so that the decreased voltage is maintained across the capacitor. Referring back to FIG. 1, this reduced voltage will cause the VCO to reduce the clock output frequency, thereby reducing the phase lead that prompted the pulsing of the down signal. Those of ordinary skill in the art will appreciate the FIG. 2 is a simplified view of the loop filter operation in that a loop filter will actually have two input nodes: a positive input node and a negative input node that are charged in a complementary fashion with respect to a common-mode voltage.
Those of ordinary skill in the art will further appreciate that PLL 100 may be configured for either a single-ended or a differential (double-ended) operation. As illustrated, PLL 100 is shown in a single-ended embodiment. However, a differential embodiment provides greater resistance to noise through its well-known common-mode rejection properties. In a differential operation, the up and down signal would each have a positive and a negative component, wherein the positive and negative components are displaced in a complementary fashion from a common-mode voltage.
Although the preceding PLL operation has had wide application, the up and down signals are inherently “bursty” in that they cannot have a duration longer than the output clock period. The abrupt changes in the up and down signals lead to “ripples” in the control voltage provided by the loop filter, thereby causing jitter in the clock output. Referring now to FIG. 3, an alternative PLL topology known as a sample-reset loop filter 300 is shown that addresses this jitter problem. This alternative PLL topology may also be denoted as a switched-capacitor frequency synthesizer. As discussed with respect to PLL 100, sample-reset loop filter includes a phase detector 140 that compares the phases of a reference clock 120 to a feedback signal 105 to generate the up and down control signals. Similarly, the feedback signal is a divided version of an output clock 110 as provided by a loop divider 130. However, instead of a VCO, a current-controlled oscillator (CCO) 310 responds to a control current 315 to adjust the frequency of the output clock. To produce the control current, a loop filter 320 includes an integration path 330 and a feed-forward path 340. The feed-forward path, which may also be denoted as a switched-capacitor ripple-smoothing filter, filters the charge provided by a charge pump B and the integrating path filters the charge provided by a charge pump A. Charge pumps A and B respond to the pulse widths of the up and down signals to alter a capacitively-stored voltage within each loop filter path as discussed analogously with respect to PLL 100. Each path includes a transconductance stage (not illustrated) that converts the respective voltages to a current. The currents from the paths are then combined to produce the control current 315 that drives the CCO. Because the capacitively-stored voltage in the proportional path 340 must be reset each sampling period with respect to the up and down pulses, a double sampling architecture may be used within the feed-forward path to provide a smoother control current that induces less jitter in the output clock. In addition, the reset circuitry is simplified in a double sampling architecture.
Although a sample-reset loop filter having a double sampling architecture in the switched-capacitor ripple-smoothing filter advantageously reduces output clock jitter, it suffers from a number of disadvantages. In particular, the design of the switched-capacitor ripple-smoothing filter is cumbersome, requiring a latency offset cancellation stage and numerous control signals. Because a latency offset cancellation stage requires delay to address the offset, ripple is worsened.
Thus, there is a need in the art for improved switched-capacitor ripple-smoothing filter designs.